What is Serial Communication? > 자유게시판

In these distributed processing networks, a variety of machines and instruments work locally, but communicate and share data or resources with one another globally using a single serial link. Thus, the master 68HC11 has only one input, MISO, which is the slave QVGA Controller’s only output. Let’s consider a simple example of an RS-485 network with one master device and two slave devices. Setting the MSTR bit initializes the 68HC11 as a master, and clearing the MSTR bit initializes it as a slave. Initializing the 68HC11 as a slave (by clearing the MSTR bit in the SPCR control register as explained below) automatically configures the /SS pin as an input. When the /SS input goes low, the slave (or QScreen in this case) transfers data in response to the SCK clock input that is initiated by the master. The /SS pin can be configured as either an input or an output. In this example, the QVGA Controller selects the serial A/D by outputting a LOW signal on /SS. The QED-Forth kernel includes pre-coded drivers that configure the SPI for maximum speed data transfer using a format that is compatible with the on-board D/A and 12 bit A/D. The QVGA Controller’s on-board 12 bit A/D and 8 bit D/A converters communicate with the processor via the SPI.

The SPI control register, SPCR, contains 8 bits which must be initialized for proper control of the QVGA Controller’s SPI (M68HC11 Reference Manual, p.8-7). It is important to note that when the CPHA bit is 0, the /SS line must be de-asserted and re-asserted between each successive data byte exchange (M68HC11 Reference Manual, p.8-3). A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.10-5) exists on the network as explained above in connection with the /SS input. If the 68HC11 is initialized as a master (by setting the MSTR bit in the SPCR control register as explained below) then bit 5 of the Port D data direction register (DDRD) determines whether /SS is an input or an output. The addressed slave unit then responds with its identification, a response identifier, a variable field and a checksum. If the 68HC11 is initialized as a master by setting the MSTR bit, then bit 5 of the Port D data direction register (PORTD.DIRECTION) determines whether /SS is an input or an output. Any required SPI output signals must be configured as outputs by setting the appropriate bits in the Port D data direction register which is named PORTD.DIRECTION in the QED-Forth kernel.

InitRS485() configures Port D to ensure that bit 5 is an output. Also, in the diagram, the master QVGA Controller’s /SS (slave select) is configured as an output. The /SS input in turn determines whether the slave responds to the SCK input, as described in a previous section. If the /SS input to a slave is inactive (high), the slave ignores the SCK input, does not transmit or receive data, and keeps its MISO output in a high-impedance state so that it does not interfere with the SPI bus. If the /SS input to a slave is active (low), the slave transfers data in response to the SCK clock input that is initiated by the master. By polling the Port A pin or by setting up an interrupt service routine, you can configure the QScreen to ignore the SCK input when /SS is high and keep MISO in a high-impedance state so that it does not interfere with the SPI bus. It provides a convenient means of connecting the QVGA Controller to a variety of peripheral devices, including analog to digital and digital to analog converters, real time clocks, and other computers which use high speed communication.

It is also an ideal choice for industrial equipment use due to its high speed, reliability and safety. Termination resistors also reduce electrical noise sensitivity due to the lower impedance. Termination resistors also reduce electrical noise sensitivity due to the lower impedance, and bias resistors are required. Consult the data sheets for any peripheral devices that you are interfacing to the SPI and, if a different configuration is needed, follow the instructions below to set up the appropriate SPI data transfer protocol. The BufferToSPI() function implements fast data transfer from a specified buffer in the controller’s memory to an SPI device. Function prototypes for this function and other versatile serial I/O routines are defined in the COMM.H header file, and are described in detail in the Control-C Glossary. RS485 is however most popularly used in programmable logic controllers and factory floors where there are lots of electrical noise. You can use the QED Board’s RS485 link to create such a multi-drop serial network. We can gain insight into the operation of the RS232 protocol by examining the signal connections used for the primary serial port in Table 9 6. The transmit and receive data signals carry the messages being communicated between the QScreen Controller and the PC or terminal.

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